The present invention relates to a method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors.
1. Related Application
A related U.S. patent application Ser. No. 09/478,037, entitled xe2x80x9cIMPLEMENTING CONTACTS FOR BODIES OF SEMICONDUCTOR-ON-INSULATOR (SOI) TRANSISTORSxe2x80x9d, by Todd Alan Christensen and John Edward Sheets II filed on Jan. 5, 2000, the same day as the present patent application.
2. Description of the Related Art
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
Silicon-on-insulator (SOI) transistors are built in a thin layer of silicon on top of a buried insulator, typically silicon dioxide, with bulk silicon below the buried insulator. FIGS. 1 and 2 illustrate a conventional SOI transistor. FIG. 1 illustrates a cross section through the width of a traditional SOI transistor. The SOI transistor has a polysilicon gate, a gate oxide over a thin silicon layer with isolation oxide, over a buried oxide, over the bulk silicon substrate. Performance of SOI transistors is increased due to reduced diffusion capacitance and due to floating body properties resulting in lower transistor threshold voltages. Since the voltage of the floating body can vary over time, the threshold voltage also varies. There are situations and circuits in which this effect is very undesirable. In these cases, there are known structures that can be used to connect the body of the SOI transistor to a known voltage. However, the known structures add much capacitance to the device, particularly gate capacitance, thus degrading the performance of these transistors so that is worse than a traditional bulk transistor. FIG. 2 illustrates a traditional body contact of a SOI transistor. Increased polysilicon area is needed to fabricate the traditional body contact. The increased polysilicon results in a large increase in capacitance of the SOI transistor, thus degrading performance.
The above-identified related patent application discloses a method for fabricating a body contact by using the bulk silicon as a connection through the buried oxide. This limits the use of a body contact to just one device type, N-channel field effect transistor (NFET) or P-channel field effect transistor (PFET) and to one voltage. A need exists for improved mechanism for implementing body contacts for silicon-on-insulator (SOI) transistors to allow connection to both NFETs and PFETs and to different voltages.
A principal object of the present invention is to provide a method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. Other important objects of the present invention are to provide such a method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors without substantial negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.